. . "De Micheli, Giovanni" . _:b7iddOtlocdOtgovauthoritiesnamesn86859611 . _:b7iddOtlocdOtgovauthoritiesnamesn86859611 _:b8iddOtlocdOtgovauthoritiesnamesn86859611 . _:b7iddOtlocdOtgovauthoritiesnamesn86859611 . _:b8iddOtlocdOtgovauthoritiesnamesn86859611 . _:b8iddOtlocdOtgovauthoritiesnamesn86859611 "De Micheli, Giovanni" . _:b11iddOtlocdOtgovauthoritiesnamesn86859611 . _:b11iddOtlocdOtgovauthoritiesnamesn86859611 . _:b11iddOtlocdOtgovauthoritiesnamesn86859611 . _:b11iddOtlocdOtgovauthoritiesnamesn86859611 "Micheli, Giovanni De" . _:b11iddOtlocdOtgovauthoritiesnamesn86859611 _:b16iddOtlocdOtgovauthoritiesnamesn86859611 . _:b16iddOtlocdOtgovauthoritiesnamesn86859611 _:b17iddOtlocdOtgovauthoritiesnamesn86859611 . _:b16iddOtlocdOtgovauthoritiesnamesn86859611 . _:b17iddOtlocdOtgovauthoritiesnamesn86859611 . _:b17iddOtlocdOtgovauthoritiesnamesn86859611 "Micheli, Giovanni De" . _:b20iddOtlocdOtgovauthoritiesnamesn86859611 . _:b20iddOtlocdOtgovauthoritiesnamesn86859611 . _:b20iddOtlocdOtgovauthoritiesnamesn86859611 . _:b20iddOtlocdOtgovauthoritiesnamesn86859611 "De Micheli, G. (Giovanni)" . _:b20iddOtlocdOtgovauthoritiesnamesn86859611 _:b25iddOtlocdOtgovauthoritiesnamesn86859611 . _:b25iddOtlocdOtgovauthoritiesnamesn86859611 _:b26iddOtlocdOtgovauthoritiesnamesn86859611 . _:b25iddOtlocdOtgovauthoritiesnamesn86859611 _:b028 . _:b26iddOtlocdOtgovauthoritiesnamesn86859611 . _:b26iddOtlocdOtgovauthoritiesnamesn86859611 "De Micheli, G." . _:b028 _:b29iddOtlocdOtgovauthoritiesnamesn86859611 . _:b028 . _:b29iddOtlocdOtgovauthoritiesnamesn86859611 . _:b29iddOtlocdOtgovauthoritiesnamesn86859611 "(Giovanni)" . "1001 $aDe Micheli, Giovanni" . . . . . . . . . . "De Micheli, Giovanni" . . . "Benini, Luca, 1967- Dynamic power management" . . . "Benini, Luca, 1967- Networks on chips" . . . "De Micheli, Giovanni Readings in hardware/software co-design" . . . "De Micheli, Giovanni Synthesis and optimization of digital circuits" . . . "Hardware/software co-design" . . . "Ku, David C., 1964- High level synthesis of ASICs under timing and synchronization constraints" . . . "Leblebici, Anil Nano-Tera.ch" . . . "Nanosystems design and technology" . . . "NATO Advanced Study Institute on \"Logic Synthesis and Silicon Compilation for VLSI Design\" (1986 : L'Aquila, Italy) Design systems for VLSI circuits" . . "n 86859611" . _:b84iddOtlocdOtgovauthoritiesnamesn86859611 . _:b84iddOtlocdOtgovauthoritiesnamesn86859611 . _:b84iddOtlocdOtgovauthoritiesnamesn86859611 "nuc86-94825: His Computer-aided synthesis of PLA-based ... 1983" . _:b84iddOtlocdOtgovauthoritiesnamesn86859611 "(hdg. on CU rept.: De Micheli, Giovanni; usage: Giovanni De Micheli)" . _:b84iddOtlocdOtgovauthoritiesnamesn86859611 "found" . _:b92iddOtlocdOtgovauthoritiesnamesn86859611 . _:b92iddOtlocdOtgovauthoritiesnamesn86859611 . _:b92iddOtlocdOtgovauthoritiesnamesn86859611 "NATO Advanced Study Institute on \"Logic Synthesis and Silicon Compilation for VLSI Design\" (1986 : L'Aquila, Italy). Design systems for VLSI circuits, 1987:" . _:b92iddOtlocdOtgovauthoritiesnamesn86859611 "CIP t.p. (G. De Micheli, Stanford University, Stanford, Calif., USA)" . _:b92iddOtlocdOtgovauthoritiesnamesn86859611 "found" . _:b100iddOtlocdOtgovauthoritiesnamesn86859611 . _:b100iddOtlocdOtgovauthoritiesnamesn86859611 . _:b100iddOtlocdOtgovauthoritiesnamesn86859611 "Hardware/software co-design, 1996:" . _:b100iddOtlocdOtgovauthoritiesnamesn86859611 "CIP t.p. (Giovanni de Micheli, Stanford U.) data sheet (b. Nov. 26, 1955)" . _:b100iddOtlocdOtgovauthoritiesnamesn86859611 "found" . _:b108iddOtlocdOtgovauthoritiesnamesn86859611 . _:b108iddOtlocdOtgovauthoritiesnamesn86859611 . _:b108iddOtlocdOtgovauthoritiesnamesn86859611 "1986-10-21T00:00:00"^^ . _:b108iddOtlocdOtgovauthoritiesnamesn86859611 "new"^^ . _:b108iddOtlocdOtgovauthoritiesnamesn86859611 . _:b115iddOtlocdOtgovauthoritiesnamesn86859611 . _:b115iddOtlocdOtgovauthoritiesnamesn86859611 . _:b115iddOtlocdOtgovauthoritiesnamesn86859611 "2009-09-04T14:53:54"^^ . _:b115iddOtlocdOtgovauthoritiesnamesn86859611 "revised"^^ . _:b115iddOtlocdOtgovauthoritiesnamesn86859611 .