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Bibframe Work

Title
Synthesis and optimization of FPGA-based systems
Type
Text
Language
English
Illustrative Content
illustrations
Classification
LCC: TK7895.G36 S58 2014 (Source: dlc)
DDC: 621.39/5 full
Identified By
Lccn: 2013958443
Content
text (Source: rdacontent)
Summary
The book is composed of two parts. The first part introduces the concepts of the design of digital systems using contemporary field-programmable gate arrays (FPGAs). Various design techniques are discussed and illustrated by examples. The operation and effectiveness of these techniques is demonstrated through experiments that use relatively cheap prototyping boards that are widely available. The book begins with easily understandable introductory sections, continues with commonly used digital circuits, and then gradually extends to more advanced topics. The advanced topics include novel techniques where parallelism is applied extensively. These techniques involve not only core reconfigurable logical elements, but also use embedded blocks such as memories and digital signal processing slices and interactions with general-purpose and application-specific computing systems. Fully synthesizable specifications are provided in a hardware-description language (VHDL) and are ready to be tested and incorporated in engineering designs. A number of practical applications are discussed from areas such as data processing and vector-based computations (e.g. Hamming weight counters/comparators). The second part of the book covers the more theoretical aspects of finite state machine synthesis with the main objective of reducing basic FPGA resources, minimizing delays and achieving greater optimization of circuits and systems.-- Source other than Library of Congress.
Table Of Contents
pt. I Design of Digital Circuits and Systems on the Basis of FPGA
1. FPGA Architectures, Reconfigurable Fabric, Embedded Blocks and Design Tools
1.1. Introduction to FPGA
1.2. The Basis of FPGA Devices
1.2.1. Configurable Logic Blocks of Xilinx FPGAs
1.2.2. Logic Elements of Altera FPGAs
1.3. Embedded Blocks
1.3.1. Embedded Memories
1.3.2. Embedded DSP Slices
1.4. Clock Distributions and Resets
1.5. Design Tools
1.6. Implementation and Prototyping
1.7. Interaction with FPGA-Based Circuits and Systems
References
2. Synthesizable VHDL for FPGA-Based Devices
2.1. Introduction to VHDL
2.2. Data Types, Objects and Operators
2.3.Combinational and Sequential Processes
2.3.1.Combinational Processes
2.3.2. Sequential Processes
2.4. Functions, Procedures, and Blocks
2.5. Generics and Generates
2.6. Libraries, Packages, and Files
2.7. Behavioral Simulation
2.8. Prototyping
References
3. Design Techniques
3.1.Combinational Circuits
3.1.1. Encoders
3.1.2. Decoders
3.1.3. Multiplexers
3.1.4.Comparators
3.1.5. Arithmetical Circuits
3.1.6. Barrel Shifters
3.2. Sequential Circuits
3.2.1. Registers
3.2.2. Shift Registers
3.2.3. Counters
3.2.4. Arithmetical Circuits with Accumulators
3.3. Finite State Machines
3.4. Optimization of FPGA-Based Circuits and Systems
3.4.1. Highly Parallel Network-Based Solutions
3.4.2. Hardware Accelerators
3.4.3. Parallel Modular Algorithms Running in Hierarchical FSMs
3.5. Design Examples for Parallel Sort
3.6. Design Examples for Parallel Search
3.7. Design Examples for Parallel Counters
3.8. Design Examples for Counting Networks
3.9. Design Examples for LUT-Based Hamming Weight Counters/Comparators
3.10. Design Examples for Operations Over Vectors
References.
4. Embedded Blocks and System-Level Design
4.1. Using IP Cores
4.2. Design with Embedded DSP Slices
4.3. Interaction with FPGA
4.3.1. Digilent Parallel Port Interface
4.3.2. UART Interface
4.4. Software/Hardware Co-design and Co-simulation
4.4.1. Software-Hardware Co-design with Digilent Parallel Port Interface
4.4.2. Software-Hardware Co-design with UART Interface
4.5. Programmable Systems-on-Chip
References
5. Design Technique Based on Hierarchical and Parallel Specifications
5.1. Modular Hierarchical Specifications
5.2. Hierarchical Finite State Machines
5.2.1. HDL Template for HFSM with Explicit Modules
5.2.2. HDL Template for HFSM with Implicit Modules
5.3. Synthesis of HFSMs
5.3.1. Synthesis of HFSMs with Explicit Modules
5.3.2. Synthesis of HFSMs with Implicit Modules
5.4. Parallel Specifications and Parallel HFSMs
5.5. Hardware Implementations of Software Programs Based on HFSM Models
5.6. Using Stacks Based on Embedded or Distributed Memories
5.7. Optimization Techniques
5.7.1. Execution of Hierarchical Returns
5.7.2. Providing Multiple Entry Points to HGSs
5.7.3. Fast Stack Unwinding
5.8. Practical Applications
References
pt. II Methods for Optimization of Finite State Machines for FPGA-Based Circuits and Systems
6. Hardware Reduction in Logic Circuits of Moore FSM
6.1. General Characteristic of Existing Methods
6.2. Object Transformation in Moore FSM
6.3. Expansion of State Codes for Moore FSM
6.4. Synthesis of Moore FSM with Replacement of Logical Conditions
References.
7. Design of FSMs with Embedded Memory Blocks
7.1. Trivial Implementation of Mealy and Moore FSMs
7.2. Structural Decomposition of FSMs
7.3. Design of Mealy FSM with Encoding of the Collections of Microoperations
7.4. Design of Mealy FSM with Encoding of the Fields of Compatible Microoperations
7.5. Design of Mealy FSM with Encoding of the Rows of Structure Table
7.6. Optimization of BIMF Based on Pseudoequivalent States of Moore FSM
References
8. Optimization of FSMs with Embedded Memory Blocks
8.1. Trivial Implementation of MP Mealy FSMs
8.2. Optimization of LUTer
8.3. Optimization of LUTer Based on Pseudoequivalent States
8.4. Optimization of LUTer Based on Encoding of Collections of Microoperations
References
9. Finite State Machines with Operational Implementation of Transitions
9.1. Conception of Operational Implementation of Transitions
9.2.Organisation of FSM with Operational Generation of Transitions
9.3. Example of FSM Design
9.4. Structural Representation of Synthesis Process for FSM with OAT
9.4.1. Base Structure of Synthesis Process for FSM with OAT
9.4.2. Refinement of Basic Structure of Synthesis Process
9.5.Organization of Operational Automaton of Transitions
9.5.1. Typical Structure Models of Operational Automata
9.5.2.Organizational Specifics of OAT
9.5.3.Organization of Combinational Part of OAT
9.6. Synthesis Method for FSM with Supplemented Set of Operations of Transitions
9.7. Investigation of Efficiency of FSM with OAT
References.
Authorized Access Point
Sklyarov, Valery, Synthesis and optimization of FPGA-based systems
Authorized Access Point Variant
Skliarova, Iouliia, Synthesis and optimization of FPGA-based systems
Barkalov, Alexander, Synthesis and optimization of FPGA-based systems
Titarenko, Larysa, Synthesis and optimization of FPGA-based systems